This AI/ML semiconductor startup who recently received over $200M in funding the past two years, is developing advanced networking hardware designed to enhance the performance and scalability of AI workloads in data centers.
They are looking for a Senior Design Verification Engineer to join their team! In this role, you will contribute across the full lifecycle of complex chip development, from microarchitecture definition to DV infrastructure and test development, to post-silicon testing.
Full time role with hybrid work schedule in the SF Bay area, Boston, or Raleigh
Job Responsibilities
- Collaborate with hardware and software architects to transform product vision into comprehensive block-level and top-level tests with high coverage.
- Utilize advanced verification techniques to address the scale and performance demands of complex devices.
- Define and implement HW/SW co-simulation infrastructure.
- Execute verification strategies to ensure prototypes meet device and system-level requirements.
Job Requirements
- 5-12 years of experience with full chip verification
- Proven industry experience and successful track record in verifying chip- and block-level RTL designs for high-performance networking or computing chips, such as Network Interface Controllers, Smart-NICs, DPUs, accelerators, and/or switches in advanced silicon geometries
- Strong current knowledge of UVM constructs, components, and practices.
- Expert knowledge of SystemVerilog, as well as Python or other scripting languages.
